VLIW Microprocessor Hardware Design: On ASIC and FPGA (Electronics)

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An application-specific instruction set processor ASIP is a component used in system-on-a-chip design.

The instruction set of an ASIP is tailored to benefit a specific application. Some ASIPs have a configurable instruction set. Usually, these cores are divided into two parts: static logic which defines a minimum ISA instruction-set architecture and configurable logic which can be used to design new instructions.

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The configurable logic can be programmed either in the field in a similar fashion to an Field-programmable gate array FPGA or during the chip synthesis. ASIPs can be used as an alternative of hardware accelerators for baseband signal processing [1] or video coding. It is very difficult to reuse the hardware datapath with handwritten finite-state machines FSM.

The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. You consent to receiving marketing messages from Indeed and may opt from receiving such messages by following the unsubscribe link in our messages, or as detailed in our terms.

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In contrast, one VLIW instruction encodes multiple operations, at least one operation for each execution unit of a device. For example, if a VLIW device has five execution units, then a VLIW instruction for the device has five operation fields, each field specifying what operation should be done on that corresponding execution unit.

Concept and Development of Modular VLIW Processor Based on FPGA

To accommodate these operation fields, VLIW instructions are usually at least 64 bits wide, and far wider on some architectures. In one cycle, it does a floating-point multiply, a floating-point add, and two autoincrement loads. All of this fits in one bit instruction:. Since the earliest days of computer architecture, [1] some CPUs have added several arithmetic logic units ALUs to run in parallel. Superscalar CPUs use hardware to decide which operations can run in parallel at runtime, while VLIW CPUs use software the compiler to decide which operations can run in parallel in advance.

Because the complexity of instruction scheduling is moved into the compiler, complexity of hardware can be reduced substantially. A similar problem occurs when the result of a parallelizable instruction is used as input for a branch. Most modern CPUs guess which branch will be taken even before the calculation is complete, so that they can load the instructions for the branch, or in some architectures even start to compute them speculatively.

VLIW microprocessor hardware design : for ASIC and FPGA, Weng Fook Lee, (electronic resource)

If the CPU guesses wrong, all of these instructions and their context need to be flushed and the correct ones loaded, which takes time. This has led to increasingly complex instruction-dispatch logic that attempts to guess correctly , and the simplicity of the original reduced instruction set computing RISC designs has been eroded.

VLIW lacks this logic, and thus lacks its energy use, possible design defects, and other negative aspects. In a VLIW, the compiler uses heuristics or profile information to guess the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch.

If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative results to preserve program semantics. Before VLIW, the notion of prescheduling execution units and instruction-level parallelism in software was well established in the practice of developing horizontal microcode. Fisher's innovations involved developing a compiler that could target horizontal microcode from programs written in an ordinary programming language. He realized that to get good performance and target a wide-issue machine, it would be necessary to find parallelism beyond that generally within a basic block.

He also developed region scheduling methods to identify parallelism beyond basic blocks. Trace scheduling is such a method, and involves scheduling the most likely path of basic blocks first, inserting compensating code to deal with speculative motions, scheduling the second most likely trace, and so on, until the schedule is complete.

COOL Chips XVII

Fisher's second innovation was the notion that the target CPU architecture should be designed to be a reasonable target for a compiler; that the compiler and the architecture for a VLIW processor must be codesigned. This was inspired partly by the difficulty Fisher observed at Yale of compiling for architectures like Floating Point Systems ' FPS, which had a complex instruction set computing CISC architecture that separated instruction initiation from the instructions that saved the result, needing very complex scheduling algorithms.

Fisher developed a set of principles characterizing a proper VLIW design, such as self-draining pipelines, wide multi-port register files , and memory architectures.


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These principles made it easier for compilers to emit fast code. The compiler was named Bulldog, after Yale's mascot. Multiflow's VLIW could issue 28 operations in parallel per instruction. The TRACE system was implemented in a mix of medium-scale integration MSI , large-scale integration LSI , and very large-scale integration VLSI , packaged in cabinets, a technology obsoleted as it grew more cost-effective to integrate all of the components of a processor excluding memory on one chip.

Multiflow was too early to catch the following wave, when chip architectures began to allow multiple-issue CPUs. Cydrome was a company producing VLIW numeric processors using emitter-coupled logic ECL integrated circuits in the same timeframe late s. This company, like Multiflow, failed after a few years. One of the licensees of the Multiflow technology is Hewlett-Packard , which Josh Fisher joined after Multiflow's demise.

These two would lead computer architecture research at Hewlett-Packard during the s.